• DocumentCode
    2620564
  • Title

    Block pipeline 2-D IIR filter structures via iteration and retiming

  • Author

    Wu, Cheng-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    1990
  • fDate
    1-3 May 1990
  • Firstpage
    731
  • Abstract
    Systolic arrays are presented for real-time 2-D infinite impulse response (IIR) filters, based on the transfer function model. Two-dimensional iteration and retiming techniques are depicted to illustrate block pipelining algorithms, which guarantee high-throughput operation for real-time applications. The systolic realizations are more regular and much faster than the previously published designs. All broadcast data lines can be eliminated, and the arrays can be fully pipelined. The retiming approach is shown to be superior to the iteration method. Examples are given for first- and second-order filters
  • Keywords
    pipeline processing; systolic arrays; two-dimensional digital filters; 2-D IIR filter structures; 2D iteration; 2D retiming; block pipelining; first order filters; high-throughput operation; iteration method; real-time applications; retiming techniques; second-order filters; systolic arrays; systolic realizations; transfer function model; Adders; Circuits; Costs; Digital filters; IIR filters; Pipeline processing; Refining; Systolic arrays; Throughput; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1990., IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Type

    conf

  • DOI
    10.1109/ISCAS.1990.112183
  • Filename
    112183