5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS

Author

Gillespie, Kevin ; Fair, Harry R. ; Henrion, Carson ; Jotwani, Ravi ; Kosonocky, Stephen ; Orefice, Robert S. ; Priore, Donald A. ; White, Jonathan ; Wilcox, Kathryn

Author_Institution

AMD, Boxborough, MA, USA

fYear

2014

fDate

9-13 Feb. 2014

Firstpage

104

Lastpage

105

Abstract

The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 29.47 mm², which includes two independent integer cores, two instruction decode units and shared instruction fetch, floating-point, and 2MB 16-way L2 cache units (Fig. 5.5.7). Along with the second instruction decode unit, this design includes a larger shared 96KB 3-way instruction cache and a 10KB L2 branch target buffer for improved single-threaded performance and multi-threaded throughput compared to a previous 32nm AMD x86-64 CPU codenamed “Bulldozer” [1].

Keywords

CMOS digital integrated circuits; CMOS integrated circuits; cache storage; microprocessor chips; AMD two-core x86-64 CPU module; AMD x86-64 CPU; Bulldozer; L2 cache units; Steamroller; high-κ metal gate bulk CMOS; instruction cache; instruction decode units; multi-threaded throughput; second instruction decode unit; size 28 nm; size 32 nm; transistors; voltage 0.8 V to 1.45 V; CMOS integrated circuits; Central Processing Unit; Clocks; Logic gates; Metals; Program processors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4799-0918-6

Type

conf

DOI

10.1109/ISSCC.2014.6757357

Filename

6757357