Electronic packaging and interconnection technology: state of the art and future developments

Author

Neugebauer, CA

Author_Institution

General Electric Corp. Res. & Dev., Schenectady, NY, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

2081

Abstract

The package bottleneck developing because of the inability to densely wire single-chip modules together on printed circuit boards is examined. It is stressed that the performance and cost of future electronic systems will strongly depend on the right choice for the packaging approach. Expected multichip-module failure mechanisms are discussed. Material requirements anticipated for future electronic packaging strategies are examined. These include wafer-scale integration, assembly of discrete packages on printed wiring boards, multichip-modules, and higher packaging levels

Keywords

VLSI; failure analysis; integrated circuit technology; modules; packaging; reliability; EMC; PCB; VLSI; corrosion; cost; deformation; discrete packages; electronic packaging; environmental stresses; high temperature sensitivity; humidity; interconnection technology; mechanical stress; multichip-module failure; noise; package bottleneck; performance; printed wiring boards; single-chip modules; wafer-scale integration; Clocks; Costs; Crosstalk; Electronics packaging; Integrated circuit interconnections; Semiconductor device packaging; Silicon; Surface-mount technology; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112203

Filename

112203