Analysis of SRAM Reliability under Combined Effect of NBTI, Process and Temperature Variations in Nano-Scale CMOS

As dimensions of MOS devices have been scaled down, new reliability problems are coming into effect. One of these emerging reliability issues is aging effects which result in device performance degradation over time. NBTI (Negative biased temperature instability) is a well known aging phenomenon which is a limiting factor for future scaling of devices. NBTI results in the generation of trapped charges which cause V_t (threshold voltage) degradation of PMOS. It is observed that a sharp V_t shift occurs in just a few seconds after turning on the MOSFET. In nano-scale CMOS technologies, process (threshold voltage) and temperature variations are also crucial reliability concerns. On the other hand, NBTI itself is dependent on temperature and threshold voltage. In this paper, the combined effect of NBTI, process and temperature variations on the reliability of the 6T SRAM (Static Random Access Memory) in 32nm CMOS technology is analyzed. It is observed that: (1) V_t abruptly increases initially and afterwards V_t shift is very small, even for prolonged time; (2) Low V_t transistors age faster than high Vt transistors; and (3) NBTI V_t degradation is more significant at higher temperature. Along with these observations, we also quantified our results in terms of number of faulty cells in SRAM array. It is observed that: (1) number of faulty cells rises over time (8.2% rise in faulty cells for the inter-die nominal Vt chip over 2 years) due to SNM degradation; (2) rise in the number of faulty cells over time due to write failures under NBTI effect is practically negligible; (3) Leakage (in the worst case condition) and access time are not impacted by NBTI.