A Novel Online Clock Skew Scheme for FPGA Based Asynchronous Wave-Pipelined Circuits

A new online clock skew scheme is proposed in this paper to improve the performance of the asynchronous wave-pipelined circuits. Previous papers implemented on wave-pipelining circuits used complex circuitry for adjusting the clock period and clock skews in offline condition. The proposed low complexity control circuit generates enable signal for enabling the output latch(s) during stable period depending on the clock speed in online condition. The proposed technique is evaluated by implementing filters using Distributed Arithmetic Algorithm (DAA) by using 3 different schemes: non-pipelining, pipelining and wave-pipelining on Altera Stratix II and Cyclone II FPGAs; 4-tap FIR filter on Stratix II and 8-tap FIR filter on Cyclone II FPGA. For the 4-tap filter implemented in Stratix II, wave-pipelined DA filter is faster by a factor of 1.36 compared to the non-pipelined one. The pipelined filter is faster by a factor of 1.38 compared to wave-pipelined one but at the cost of increased logic utilization by 115.69%. For the 8-tap filter implemented in Cyclone II, wave-pipelined DA filters is faster by a factor of 1.40 compared to the non-pipelined one. The pipelined filter is faster by a factor of 2.14 compared to wave-pipelined one but at the cost of increased registers by 569.69% and LEs by 74.9%. The dynamic power for the 4-tap DA wave-pipelined filter implemented in Stratix II is less by approx. 8% compared to pipelined and greater by approx. 28% compared to non-pipelined circuits.