Title :
An accurate and efficient delay model for CMOS gates in switch-level timing analysis
Author :
Lin, Shen P. ; Marek-Sadowska, Malgorzata
Author_Institution :
Electron. Res. Lab., California Univ., Berkeley, CA, USA
Abstract :
A heuristic switch-level model for calculating the gate delay is described. It is high accuracy due to its SPICE-like integration approach. Only linear circuit elements are considered, resulting in high efficiency. An easy approach for taking the gate-to-source and gate-to-drain capacitances of MOS transistors into consideration is proposed. An effective way to determine the time step is introduced. Preliminary tests indicate that the model is very accurate and fast, which makes it suitable for handling very large designs. Preliminary timing results for several complex CMOS gates show very good accuracy
Keywords :
CMOS integrated circuits; circuit analysis computing; insulated gate field effect transistors; linear network analysis; CMOS gates; MOS transistors; SPICE-like integration approach; accuracy; delay model; gate delay; gate-to-drain capacitances; gate-to-source capacitances; heuristic switch-level model; linear circuit elements; switch-level timing analysis; time step; Capacitors; Circuits; Delay estimation; MOSFETs; Resistors; SPICE; Semiconductor device modeling; Switches; TV; Timing;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112220
