Clock skew elimination in CMOS VLSI

An optimization-based method of eliminating the clock skews arising from interconnect delays is described. Also described are algorithms for selecting the best buffer sizes to eliminate the interconnect related skew, assuming the clock distribution network can be modeled as an RC tree. Skew elimination is shown to be a constrained minimization problem. The equations which determine the optimal buffer sizes are derived, the methods for solving them are discussed, and implementation details are given