Estimating and optimizing RC interconnect delay during physical design

During the physical design process, prior to detailed routing, it is desired to bound the interconnect delay based on the bounding box of the pins on the net, horizontal, and vertical estimates of interconnect capacitance and resistance per length and estimate the pin-to-pin delays based on the positions of the pins inside and on the bounding box. Assuming the interconnect will be routed based on a rectilinear Steiner tree (RST), the work of F.K. Chung and F.H. Hwang (1979) is used to bound the size of the largest and smallest possible RSTs given the bounding-box of the pins on the net (this is done for nets with ⩽10 pins or with a number of pins that is the square of a number). Bounds can then be derived for the RC interconnect delay by observing that the Elmore delay expression for a net consists of two parts: a term that is a function of the output drive resistance and total net capacitance, and a term that is a function of the net topography (resistive characteristics of the final RC interconnect tree). Using the internal net pin positions and knowledge of which pins are associated with the outputs and input of the RC tree, individual pin-to-pin delay estimates can be made prior to the existence of the final route. The RC delay estimation techniques are incorporated into Allegro, a performance-driven placement program for cell-based ICs that optimizes path delay and total wirelength using an approach based on linear programming