Title :
Performance-driven layout of CMOS VLSI circuits
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana-Champaign, IL, USA
Abstract :
As design rules get scaled down to submicron dimensions, physical CAD tools need to be much more performance-driven as opposed to purely geometry-driven. For instance, to help prevent timing bottlenecks, it is necessary to consider timing-critical nets during circuit partitioning, placement, and routing phases. Long parallel lines can cause crosstalk problems; therefore, it is prudent to limit the length of parallel runners, especially in high-speed circuit layout. The issues are even more complex in active circuit layout. For sensitive analog circuits or clock distribution circuits, various symmetry constraints need to be met. Recent developments in performance-driven layout techniques are reviewed, and these newly emerging issues are discussed
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; crosstalk; CMOS VLSI circuits; active circuit layout; circuit partitioning; clock distribution circuits; crosstalk problems; design rules; high-speed circuit layout; parallel runners; performance-driven layout techniques; physical CAD tools; placement; routing phases; submicron dimensions; symmetry constraints; timing bottlenecks; timing-critical nets; CMOS technology; Chip scale packaging; Circuits; Design automation; Design engineering; Parameter estimation; Productivity; Programmable logic arrays; Read only memory; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112229