A first-order current-steering sigma-delta modulator

Summary form only given, as follows. A new architecture is presented for a first-order sigma-delta modulator. The system can operate at a high sampling frequency, can be used as a building block for higher-order modulators, and employs circuit techniques that are largely technology-independent. The system was realized in a 2-μm n-well, double-metal single-poly CMOS technology. The circuit occupies an area of 1580×580 μm². It has a measured resolution of 9 b and a linearity of 13 b at a clock frequency of about 20 MHz and an oversampling ratio of 128. It operates from a power supply of ±2.5 V with a power consumption of 3 mW