Title :
WASP: a wafer-scale massively parallel processor
Author_Institution :
Aspex Microsyst. Ltd., Brunel Univ., Uxbridge, UK
Abstract :
The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; fault tolerant computing; integrated circuit technology; parallel architectures; CMOS; Massively Parallel Processors; TOPS; Tera Operations-Per-Second; WASP; WSI associative string processor; architectural requirements; cost-effectiveness; engineering requirements; fault-tolerant WSI MPP architecture; wafer-scale massively parallel processor; Application software; Automotive engineering; Computer networks; Concurrent computing; Costs; Data communication; Packaging; Parallel processing; Power engineering and energy; Power engineering computing;
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
DOI :
10.1109/ICWSI.1990.63880
