A fast binary front-end ASIC for the RICH detector of the COMPASS experiment at CERN

The paper describes a fast binary integrated circuit. The chip was developed to read-out the multi-anode photomultiplier tubes which equip the RICH detector of the COMPASS experiment at CERN. The ASIC incorporates eight identical channels, each featuring a low-noise amplifier followed by a comparator and a LVDS driver. The amplifier has a peaking time of 10 ns and a gain programmable from 0.4 mV/fC to 4.8 mV/fC. Two 10-bits Digital-to-Analogue Converters per channel allow independent settings of the amplifier baseline and of the discriminator threshold. The circuit works with a minimum threshold of 3 fC and handles hit rates in excess of 5 MHz per channel. Implemented in a 0.35 μm CMOS process, the chip dissipates 200 mW from a 3.3 V power supply. After the prototyping phase, six 8-inch wafers have been produced and are under test. The new front-end electronics will be installed in the experiment before the 2009 data taking.