9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal-area-network (WPAN) applications. RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs [1], all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability [2]. However, analog PLLs dominate the field of ULP WPAN radios [1], since the time-to-digital-converter (TDC) of an ADPLL has traditionally been power hungry. We present a 2.1-to-2.7GHz 860μW fractional-N ADPLL in 40nm CMOS for WPAN applications, which breaks the 1mW barrier and consumes at least 5× lower power compared to state-of-the-art ADPLLs.