L-band on-chip matching Si-MMIC low noise amplifier fabricated in SOI CMOS process

Author

Ono, M. ; Suematsu, N. ; Yamaguchi, Y. ; Ueda, K. ; Komurasaki, H. ; Kubo, S. ; Iyama, Y. ; Ishida, O.

Author_Institution

Inf. Technol. R&D Centre, Mitsubishi Electr. Corp., Kanagawa, Japan

fYear

1998

fDate

18-18 Sept. 1998

Firstpage

90

Lastpage

93

Abstract

In this paper, on-chip matching Si-MMIC low noise amplifier (LNA) was fabricated in a 0.35 /spl mu/m SOI CMOS process. This LNA offers 8.7 dB gain, 4.2 dB NF, -2 dBm IIP3 at 2.1 GHz with 3 V, 3 mA DC power. The reduction of the dielectric loss of the spiral inductor is also discussed by referring to the extraction result of the equivalent circuit parameter.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; UHF amplifiers; UHF integrated circuits; elemental semiconductors; equivalent circuits; impedance matching; inductors; integrated circuit noise; silicon; silicon-on-insulator; 0.35 micron; 2.1 GHz; 3 V; 3 mA; 4.2 dB; 8.7 dB; L-band low noise amplifier; SOI CMOS process; Si; Si MMIC LNA; dielectric loss; equivalent circuit; on-chip matching; spiral inductor; CMOS process; Circuits; Dielectric losses; Dielectric substrates; Inductors; L-band; Low-noise amplifiers; Parasitic capacitance; Spirals; Stripline;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 1998. Digest of Papers. 1998 Topical Meeting on

Conference_Location

Ann Arbor, MI, USA

Print_ISBN

0-7803-5288-2

Type

conf

DOI

10.1109/SMIC.1998.750200

Filename

750200