Title :
BIST for testing of delay
Author :
Milor, Linda ; Jia, Cheng
Author_Institution :
Georgia Inst. of Technol., Atlanta
Abstract :
A circuit has been designed to determine if on-chip path delays are equal to a pre-specified target. The circuit uses a delay-locked loop to generate the target delay, combined with a phase detector to determine the delay of a path in comparison with this target delay. The circuit was implemented with 0.18 um CMOS and has been analyzed over process, supply, and temperature variations. Accuracies in delay detection are within 200 ps.
Keywords :
CMOS digital integrated circuits; built-in self test; delay lock loops; phase detectors; BIST; CMOS; delay detection; delay-locked loop; on-chip path delay testing; phase detector; size 0.18 mum; Built-in self-test; Circuits; Clocks; Delay; Detectors; Phase detection; Pulse measurements; Pulse shaping methods; Testing; Voltage;
Conference_Titel :
Advances in Sensors and Interface, 2007. IWASI 2007. 2nd International Workshop on
Conference_Location :
Bari
Print_ISBN :
978-1-4244-1245-7
Electronic_ISBN :
978-1-4244-1245-7
DOI :
10.1109/IWASI.2007.4420031
