Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection

This paper presents a low-power embedded LDPC-H.264 decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). This method is developed for H.264 layered (data partitioned) video transmission over Low Density Parity Check (LDPC) codec. We exploit the fact that not all transmitted data require the same level of error protection; this is known as unequal error protection (UEP). In particular, we use variable iteration LDPC decoding along with H.264 data partitioning (DP). In this scheme, we determine and use the lowest values of iterations that are needed by the decoder to achieve pre-specified image qualities at the receiver, and apply DVFS to minimize power.