FPGA implementation of a new hybrid modulation strategy for a modified dual bridge multilevel dc-link inverter topology

Author

Thamizharasan, S. ; Baskaran, J. ; Kamalsakthi, S.

Author_Institution

Surya Group of Instn., Villupuram, India

fYear

2014

fDate

16-17 April 2014

Firstpage

518

Lastpage

523

Abstract

The paper evolves a new hybrid modulation strategy to incarnate a higher quality sinusoidal output voltage from a modified dual bridge multilevel dc-link inverter (DBMLDCLI) topology. The scheme is developed to minimize the switching loss in power devices. The proposed modulation strategy is derived from the fundamental switching and pulse width modulation (PWM) through modified sinusoidal reference function. The VHDL algorithm is suitably developed to imbibe the proposed modulation strategy and simulated in Modelsim software. The proposed algorithm is implemented in Xilinx spartan3E-500 FG 320 processor and the simulation results accorded with the experimental results.

Keywords

PWM invertors; field programmable gate arrays; hardware description languages; multivalued logic circuits; network topology; DBMLDCLI topology; FPGA implementation; Modelsim software; PWM; VHDL algorithm; Xilinx spartan3E-500 FG 320 processor; dual bridge multilevel dc-link inverter topology; hybrid modulation strategy; modified sinusoidal reference function; power devices; pulse width modulation; switching loss; Computational modeling; Field programmable gate arrays; Harmonic analysis; Inverters; Power system harmonics; Pulse width modulation; Semiconductor device modeling; Field Programmable Gate Array (FPGA); Multilevel dc link inverter (MLDCLI);

fLanguage

English

Publisher

ieee

Conference_Titel

Computation of Power, Energy, Information and Communication (ICCPEIC), 2014 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-3826-1

Type

conf

DOI

10.1109/ICCPEIC.2014.6915418

Filename

6915418