15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO

Due to the high supply sensitivity of ring voltage-controlled oscillators (RVCOs) ([oscillation frequency change %] / [V_DD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the voltage dropout of an LDO consumes extra power and voltage headroom, which is unacceptable in low-voltage design. Moreover, the device noise from the LDO degrades the phase-noise performance. Recently published works [1-5] employ analog compensation techniques to lower supply sensitivity, and [2] incorporates a hybrid background calibration scheme for robustness. However, the additional current sources and active devices embedded in the oscillator [1-5] increase power and noise. In this work, a DCO with passive devices and all-digital calibration mitigates supply sensitivity under PVT variation, while maintaining phase noise and power consumption. The digital background-calibration logic regulates the oscillator supply to an optimally insensitive point by monitoring a digital loop filter (DLF) code, leveraging an advantage of an ADPLL [6].