DocumentCode :
2622955
Title :
Time to digital converter implementation on a configurable digital processor for BaF2 scintillation detector events
Author :
Scarpaci, S. ; Brambilla, S. ; Camera, F. ; Geraci, A. ; Million, B. ; Riboldi, S. ; Cuccarese, M. ; Caramanno, S.
Author_Institution :
Politecnico di Milano - Dept. of Electronics, via C.Golgi 40, 20133, Italy
fYear :
2008
fDate :
19-25 Oct. 2008
Firstpage :
2006
Lastpage :
2009
Abstract :
The paper presents a configurable analog-digital processor handling scintillator BaF2 signals. It is composed of a VME mother-board housing two analog sections that accomplish analog conditioning of the detector signals. The processing core is split between two digital configurable devices, i.e. a FPGA XC4VSX35 and a DSP TMS C6203.
Keywords :
Analog-digital conversion; Delay lines; Detectors; Digital signal processing; Field programmable gate arrays; Nuclear electronics; Scintillation counters; Signal detection; Signal processing; Signal resolution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE
Conference_Location :
Dresden, Germany
ISSN :
1095-7863
Print_ISBN :
978-1-4244-2714-7
Electronic_ISBN :
1095-7863
Type :
conf
DOI :
10.1109/NSSMIC.2008.4774775
Filename :
4774775
Link To Document :
بازگشت