A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

This work presents a high performance half pixel interpolation unit for the H.264/AVC standard. The presented architecture is able to process very high definition videos (3840 × 2048 pixels) at real time processing (30 frames per second), and can be integrated in a complete motion estimation architecture without limiting the other modules´ performance. It also presents a novel arrangement of interpolated samples which makes simple the search for the best fractional motion vector. The architecture was described in VHDL and synthesized to a Xilinx Virtex4 FPGA, and it achieved the best results when compared to related works published in the literature.