DocumentCode :
2623314
Title :
Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections
Author :
Ginez, O. ; Portal, J.M. ; Muller, Ch.
Author_Institution :
IM2NP-UMR, Univ. de Provence (Aix-Marseille I), Marseille, France
fYear :
2009
fDate :
25-29 May 2009
Firstpage :
61
Lastpage :
66
Abstract :
Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive states depending upon the material nature integrated in memory element. To lead such memory concept to a memory circuit or even, to a product, a big effort has to be done to forecast tools necessary to design and test this emerging memory. In this paper, a particular technology of ReRAM memories is introduced. First, an electrical model (ELDO-like) of a MIM-based (Metal/Insulator/Metal) ReRAM memory element is presented. Then, this model is used for the robustness assessment of ReRAM memory element in presence of actual defects inherent to CMOS process steps. Based on this electrical model, a big hurdle has been broken between material physics, design and test. Thus, new methods and solutions could be developed in the field of design and test for ReRAM memories.
Keywords :
CMOS memory circuits; flash memories; random-access storage; switching circuits; CMOS process; EEPROM; conventional charge storage-based devices; defect injections; defects; electrical model; flash memory; metal-insulator-metal memory element; nonvolatile memory; resistive switching RAM; resistive switching memory; robustness assessment; CMOS technology; Circuit testing; EPROM; Integrated circuit technology; Metal-insulator structures; Nonvolatile memory; Random access memory; Read-write memory; Semiconductor device modeling; Voltage control; Defect Injection; Electrical Simulation; Memory Testing; ReRAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2009 14th IEEE European
Conference_Location :
Seville
Print_ISBN :
978-0-7695-3703-0
Type :
conf
DOI :
10.1109/ETS.2009.23
Filename :
5170460
Link To Document :
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