Title :
Partial Scan Approach for Secret Information Protection
Author :
Inoue, Michiko ; Yoneda, Tomokazu ; Hasegawa, Muneo ; Fujiwara, Hideo
Author_Institution :
Nara Inst. of Sci. & Technol.(NAIST), Ikoma, Japan
Abstract :
This paper proposes a secure scan design method which protects the circuits containing secret information such as cryptographic circuits from scan-based side channel attacks.The proposed method prevents the leakage of secret information by partial scan design based on a balanced structure. We also guarantee the testability of both the design under test and DFT circuitry, and therefore, realize both security and testability. Experiments for RSA circuit shows the effectiveness of the proposed method.
Keywords :
circuit testing; discrete Fourier transforms; logic design; public key cryptography; sequential circuits; DFT circuitry; RSA circuit; design under test; partial secure scan approach; scan-based side channel attack; secret information protection; sequential circuit; Authentication; Circuit testing; Cryptography; Design methodology; Information security; Kernel; Logic testing; Protection; Registers; Sequential circuits; Balanced structure; Cryptographic circuits; Security; Testability;
Conference_Titel :
Test Symposium, 2009 14th IEEE European
Conference_Location :
Seville
Print_ISBN :
978-0-7695-3703-0
DOI :
10.1109/ETS.2009.15
