DocumentCode
2623661
Title
An optimized label-broadcast parallel algorithm for connected components labeling
Author
Teixeira, Joao Marcelo Xavier Natário ; Reis, Bernardo ; Teichrieb, Veronica ; Kelner, Judith
Author_Institution
Virtual Reality & Multimedia Res. Group, Fed. Univ. of Pernambuco, Recife, Brazil
fYear
2010
fDate
24-26 March 2010
Firstpage
99
Lastpage
104
Abstract
This paper presents a simple and fast algorithm for labeling connected components in binary images, based on a parallel label-broadcast paradigm. A grid of processing units (called spiders) is used and each element is responsible for updating its label value, during a specific number of iterations. We describe the design and implementation of an embedded architecture for real-time labeling of black and white images based on FPGA technology. Since the image is divided and processed independently by processing elements, it is possible to use the proposed algorithm in an FPGA platform attached to an image sensor and have a focal plane processor circuit-like.
Keywords
field programmable gate arrays; image processing; image sensors; parallel algorithms; peripheral interfaces; FPGA technology; binary images; embedded architecture; focal plane processor; image sensor; label value; label-broadcast parallel algorithm; labeling connected components; processing elements; processing units; real-time labeling; spider grid; Algorithm design and analysis; Application software; Field programmable gate arrays; Hardware; Iterative algorithms; Labeling; Parallel algorithms; Parallel processing; Pixel; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic Conference (SPL), 2010 VI Southern
Conference_Location
Ipojuca
Print_ISBN
978-1-4244-6309-1
Type
conf
DOI
10.1109/SPL.2010.5483030
Filename
5483030
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