A low-power-consumption, supply-noise-insensitive charge pump PLL with a voltage regulator for on-chip clock generating in MAPS at STAR experiment

In this paper, a low power consumption and high supply noise immunity CMOS charge pump phase-locked loop (PLL) is presented. This PLL will be used for on-chip clock generation in monolithic active pixel sensor (MAPS) for the Solenoidal Tracker at RHIC (STAR). The PLL equips a voltage regulator which provides two stable power supplies to the charge pump (CP) and the voltage-controlled oscillator (VCO) respectively, generating a 160 MHz clock with a jitter level of less than 100 ps RMS from 10 MHz reference clock. By using virtual grounded cascode compensation technique and connection in series, the voltage regulator achieves a maximum PSNR (Power Supply Noise Rejection) of −40 dB over the entire frequency spectrum. The circuit is fabricated in a 0.35 um standard CMOS process and power consumption is 7 mW at 160 MHz.