DocumentCode :
262378
Title :
19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology
Author :
Fackenthal, Richard ; Kitagawa, Makoto ; Otsuka, Wataru ; Prall, Kirk ; Mills, D. ; Tsutsui, K. ; Javanifard, Jahanshir ; Tedrow, Kerry ; Tsushima, Tomohito ; Shibahara, Yoshiyuki ; Hush, Glen
Author_Institution :
Micron, Folsom, CA, USA
fYear :
2014
fDate :
9-13 Feb. 2014
Firstpage :
338
Lastpage :
339
Abstract :
Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (<;1Gb) while those reporting high-density arrays (>8Gb) were accompanied by relatively low read and write performance [1-5]. This work describes a 16Gb ReRAM designed in a 27nm node, with a 1GB/s DDR interface and an 8-bank concurrent DRAM-like core architecture. High parallelism, a pipelined data-path architecture and innovations such as concurrent set/reset verify combine to achieve 200MB/s write and 1GB/s read throughputs in a high-density device.
Keywords :
DRAM chips; memory architecture; pipeline processing; DDR interface; DRAM-like core architecture; ReRAM design; bit rate 1 Gbit/s; bit rate 200 Mbit/s; flash memories; high-density array; low density array; pipelined data-path architecture; resistive RAM; size 27 nm; storage capacity 16 Gbit; Computer architecture; Microprocessors; Programming; Sensors; Throughput; Tiles; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4799-0918-6
Type :
conf
DOI :
10.1109/ISSCC.2014.6757460
Filename :
6757460
Link To Document :
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