Title :
A novel design of an asymmetric D-latch
Author :
Trotta, S. ; Sundermeyer, J. ; Weber, N. ; Saurer, J.
Author_Institution :
Fraunhofer IIS, Erlangen, Germany
Abstract :
The paper discusses design aspects of high speed asymmetric D-latches. It is shown how an asymmetric input clock signal can be used favorably to improve latch performance. Moreover. a completely asymmetric D-flipflop, which shows a static behavior at low frequency and a superdynamic behavior at very high speed, is presented.
Keywords :
current-mode circuits; flip-flops; integrated circuit design; network topology; asymmetric input clock signal; completely asymmetric D-flipflop; current mode latches; high speed D-latch; high speed asymmetric D-latch; network topology; pseudo random bit sequence generator IC; static behavior; superdynamic behavior; Clocks; Current density; Frequency conversion; Latches; Legged locomotion; Logic; Negative feedback loops; RF signals; Switches; Tail;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems, 2004. Digest of Papers. 2004 Topical Meeting on
Print_ISBN :
0-7803-8703-1
DOI :
10.1109/SMIC.2004.1398218
