FPGA-Based Fast Detection With Reduced Sensor Count for a Fault-Tolerant Three-Phase Converter

Fast fault detection (FD) and reconfiguration is necessary for fault tolerant power electronic converters in safety critical applications to prevent further damage and to make the continuity of service possible. The aim of this study is to minimize the number of the used additional voltage sensors in a fault tolerant three-phase converter. In this paper, first a practical implementation of a very fast FD scheme with reduced sensor number is discussed. Then, an optimization in this scheme is also presented to decrease the detection time. For FD, special time and voltage criterion are applied to observe the error in the estimated phase-to-phase voltages for a specific period of time. The proposed optimization is based on the fact that following a detectable fault, two line-to-line voltages will deviate from their respective estimated values. Fault detection is studied for a three-leg two-level fault tolerant converter. Control and FD systems are implemented on a single field-programmable gate array. First, hardware in the loop experiments are carried out to evaluate the implemented schemes. Then, fully experimental tests are performed. The results confirm good performance of the proposed detection schemes, the digital controller and the fault tolerant structure. It is shown that such methods can detect and locate a fault in a few tens of microseconds. In certain cases the optimized scheme can be faster up to 50%, and in the other cases they have the same detection time.