Title :
A new short circuit power model for complex CMOS gates
Author :
Wang, Qi ; Vrudhula, Sarma B K
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
In this paper we propose a new model for short circuit power estimation of CMOS gates. The short circuit power of a CMOS gate is estimated by converting the gate into an equivalent CMOS inverter and all input signal waveforms into a single equivalent input signal for the inverter. The channel width and the input to the equivalent inverter are functions of the waveforms of all the inputs. This is different from the traditional approaches where only worst case situations are considered. HSPICE simulation of NAND gates using a commercial 0.25 μm CMOS process shows that the proposed new short circuit power model for CMOS gates is much more accurate than previously reported models
Keywords :
CMOS logic circuits; NAND circuits; SPICE; circuit simulation; equivalent circuits; integrated circuit modelling; logic gates; HSPICE simulation; NAND gates; channel width; complex CMOS gates; equivalent CMOS inverter; equivalent input signal; input signal waveforms; short circuit power model; worst case situations; CMOS digital integrated circuits; CMOS process; CMOS technology; Circuit simulation; Delay estimation; Inverters; Low power electronics; MOSFETs; Power dissipation; Semiconductor device modeling;
Conference_Titel :
Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on
Conference_Location :
Como
Print_ISBN :
0-7695-0019-6
DOI :
10.1109/LPD.1999.750409
