A Hierarchical Architecture of N-Port Memory Based on FPGA

As FPGAs grow in logic capacity, they are being used to implement entire systems which require large amount of storage. Most commercial devices implement on-chip storage by providing several large arrays embedded into the FPGA. Scholars have done some research on implementing user logic memory models with single-port and dual-port physical arrays. However, their work is based on the assumption that user memory models are either single-port or dual- port. Thus, we need an efficient way to implement import memory on FPGA considering that most FPGA vendors do not provide N-port physical arrays (Nges3). In this paper, a novel hierarchical N-port memory architecture, which fits LUT-based FPGAs, is proposed. The principle of hierarchical architecture is mapping distributed memory resources of LUT as l-port Memory Banks. Data in different Memory Banks can be accessed simultaneously. Besides, extend port importance hierarchy (EPIH) algorithm is proposed for basic conflict handling, while block access control (BAC) algorithm is proposed for reducing conflict when processors carry block read/write. Experiment on Xilinx Virtex-II chips shows that this design saves almost 88% LUT resources compared to implementation of N ports in each memory cell.