Efficient power estimation techniques for HW/SW systems

We present a power estimation framework for hardware/software System-On-Chip (SOC) designs based on concurrent and synchronized execution of a hardware simulator and an instruction set simulator. Concurrent execution of the simulators for different parts of the system is necessary to obtain accurate input and execution traces, and hence accurate power estimates. However, as in the case of hardware/software co-simulation, the communication and synchronization between the various simulators causes significant overhead. We describe two speedup techniques for addressing this issue-energy caching and power macromodeling-that present interesting accuracy vs. efficiency tradeoffs