22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

High-speed low-resolution ADCs are widely used for various applications, such as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, which is often required in feedback-loop systems. However, the area and power consumption are exponentially increased by increasing the resolution since the number of comparators must be 2^N. A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers. However, the conventional folding amplifiers consume a large amount of power to realize a fast response. In contrast, a folding ADC with only dynamic power consumption and without using amplifiers is reported in [3]. However, only a folding factor of 2 is realized, and therefore the number of comparators is reduced by half.