Author :
Song, S.C. ; Zhang, Z.B. ; Hussain, M.M. ; Huffman, C. ; Barnett, J. ; Bae, S.H. ; Li, H.J. ; Majhi, P. ; Park, C.S. ; Ju, B.S. ; Park, H.K. ; Kang, C.Y. ; Choi, R. ; Zeitzoff, P. ; Tseng, H.-H. ; Lee, B.H. ; Jammy, R.
Abstract :
This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack
Keywords :
MOSFET; high-k dielectric thin films; low-power electronics; semiconductor device manufacture; semiconductor device reliability; 45 nm; LSTP; dual high-k CMOSFET; dual metal gate CMOS integration; low stand-by power; CMOSFETs; Dry etching; Electrodes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOS devices; MOSFETs; Manufacturing; Wet etching;
