Title :
A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond
Author :
Park, Ki-Tae ; Choi, Jungdal ; Sel, Jongsun ; Kim, Viena ; Kang, Changseok ; Shin, Yoocheol ; Roh, Ukjin ; Jintaek Park ; Jang-Sik Lee ; Sim, Jaesung ; Jeon, Sanghun ; Changhyun Lee ; Kinam Kim
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin
Abstract :
A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements
Keywords :
NAND circuits; flash memories; integrated memory circuits; 40 nm; NAND flash memory; NAND memory cell; asymmetric source-drain structure; inversion layer; short channel effect; Cellular phones; Circuit synthesis; Consumer electronics; Cost function; Coupling circuits; Digital audio players; Interference; Nonvolatile memory; Research and development; Silicon compounds;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705196
