23.8 A 34V charge pump in 65nm bulk CMOS technology

Recent advances in MEMS-based oscillators have resulted in their proliferation in timing applications that were once exclusive to quartz-based devices [1]. For applications requiring low phase noise - e.g., cellular, GPS and high-speed serial links - one possible approach is to bias the MEMS resonator at a higher DC voltage to reduce its motional impedance and increase signal energy [2]. Realizing high-voltage charge pumps in bulk CMOS technology is limited by the breakdown voltage of the well/substrate diodes shown in Fig. 23.8.1(a) and Fig. 23.8.1(b). This breakdown limit is even lower with technology scaling and is <;10V in a 22nm CMOS node. Systems with high-voltage requirements often resort to older, high-voltage-tolerant nodes or exotic technologies that limit MEMS integration into SoCs. This work demonstrates a charge pump design in 65nm technology with a three-fold increase in the output voltage range. Highvoltage tolerance is enabled by the proposed well-biasing arrangement and oxide isolation. The pump achieves 34V output by using three different charge pump cells that tradeoff achievable voltage range and power efficiency to achieve a peak efficiency of 38%. Additionally, finger capacitors are optimized to ensure reliability while maintaining efficiency.