Investigation of FinFET Devices for 32nm Technologies and Beyond

FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vt´s are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious challenge due to poly-to-active overlay requirements and the need for raised S/D for series resistance reduction. A new FinFET design without S/D contact pads is thus proposed and a selective epitaxial process to merge individual fins is developed