Investigation of FinFET Devices for 32nm Technologies and Beyond

Author

Shang, H. ; Chang, L. ; Wang, X. ; Rooks, M. ; Zhang, Y. ; To, B. ; Babich, K. ; Totir, G. ; Sun, Y. ; Kiewra, E. ; Ieong, M. ; Haensch, W.

Author_Institution

IBM Semicond. R&D Center, T. J. Watson Res. Center, Yorktown Heights, NY

fYear

0

fDate

0-0 0

Firstpage

54

Lastpage

55

Abstract

FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vt´s are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious challenge due to poly-to-active overlay requirements and the need for raised S/D for series resistance reduction. A new FinFET design without S/D contact pads is thus proposed and a selective epitaxial process to merge individual fins is developed

Keywords

MOSFET; electron beam lithography; nanotechnology; 20 nm; 32 nm; FinFET devices; S/D contact pads; e-beam lithography; fin pitch; selective epitaxial process; Contact resistance; Epitaxial growth; Fabrication; FinFETs; Lithography; Scattering; Silicidation; Silicides; Space technology; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705213

Filename

1705213