Author :
Chen, Xia ; Fang, Shao-Yun ; Gao, Wenzhong ; Dyer, T. ; Teh, Y.W. ; Tan, S.S. ; Ko, Y. ; Baiocco, C. ; Ajmera, A. ; Park, Jongho ; Kim, Jung-Ho ; Stierstorfer, R. ; Chidambarrao, D. ; Luo, Zhengqian ; Nivo, N. ; Nguyen, P. ; Yuan, Jiaxin ; Panda, Siddhart
Abstract :
Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET Ion=660muA/mum at Ioff=100nA/mum at 1V Vdd operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT
Keywords :
Ge-Si alloys; MOSFET; nanotechnology; 1 V; 45 nm; PFET; SiGe; dual stress liner; inverter ring oscillator delay; poly gate pitch devices; salicidation; semiconductor junctions; stress proximity technique; Capacitive sensors; Compressive stress; DSL; Germanium silicon alloys; Research and development; Semiconductor device manufacture; Silicon germanium; Space technology; Surface-mount technology; Tensile stress;
