1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Author

Grudowski, Paul ; Adams, Vance ; Bo, Xiang-Zheng ; Loiko, Konstantin ; Filipiak, Stan ; Hackenberg, John ; Jahanbani, Mo ; Azrak, Marijean ; Goktepeli, Sinan ; Shroff, Mehul ; Liang, Wen-Jya ; Lian, S.J. ; Kolagunta, Venkat ; Cave, Nigel ; Wu, Chi-Hsi ; F

Author_Institution

Austin Silicon Technol. Solutions, Freescale Semicond., Inc., Austin, TX

fYear

0

fDate

0-0 0

Firstpage

62

Lastpage

63

Abstract

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary

Keywords

CMOS integrated circuits; MOSFET; SPICE; nanotechnology; oscillators; semiconductor device models; silicon-on-insulator; 1D geometry effects; 2D boundary effects; 65 nm; PMOS; SOI technology; SPICE models; circuit design; dESL boundary; dual etch stop layer stressors; ring oscillator; CMOS technology; Compressive stress; Etching; Geometry; MOS devices; Performance gain; Semiconductor films; Silicon; Solid modeling; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705217

Filename

1705217