Title :
Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation
Author :
Ota, Kaoru ; Sanuki, T. ; Yahashi, K. ; Miyanami, Y. ; Matsuo, Kenshi ; Idebuchi, J. ; Moriya, M. ; Nakayama, Keisuke ; Yamaguchi, Ryo ; Tanaka, Hiroya ; Yamazaki, Tsutomu ; Terauchi, S. ; Horiuchi, A. ; Fujita, S. ; Mizushima, Ichiro ; Yamasaki, Hirofumi
Author_Institution :
SONY Corp., Kanagawa
Abstract :
We developed a less layout-dependent epitaxially grown SiGe (eSiGe) source/drain (S/D) technique for pFET. We found that the effective stressor region of eSiGe existed only near the channel and that the volume effect of eSiGe was small. On the basis of this mechanism, a new recess RIE and a new epitaxial growth technology were developed, so that the gate-pitch dependence, S/D length dependence and channel width dependence were extremely reduced. In addition, we succeeded in increasing the drive current by improving the eSiGe structure and the impurity profile. We also obtained a high drive current of 750 muA/mum at Vdd=1V, Ioff=100nA/mum
Keywords :
MOSFET; epitaxial growth; nanotechnology; semiconductor epitaxial layers; 1 V; 45 nm; SiGe; epitaxial growth technology; pFET; recess RIE; source/drain technique; Companies; Epitaxial growth; Etching; Germanium silicon alloys; Impurities; Large scale integration; Manufacturing processes; Semiconductor device manufacture; Silicon germanium; Stress;
Conference_Titel :
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
1-4244-0005-8
DOI :
10.1109/VLSIT.2006.1705218
