Hardware implementation of delay-coded spiking-RBF neural network for unsupervised clustering

In this paper we describe a novel, hardware implementation friendly model of spiking neurons, with "sparse temporal coding". This is used then to implement a neural network on a FPGA platform, yielding a high degree of parallelism. In the first section of this paper the biological background of spiking neural networks are discussed such as the structure and the functionality of natural neurons which form the basis of the further presented, artificially built ones. With a clustering application in mind, we prove, that input patterns can be encoded in the synaptic weights by local Hebbian delay-learning where, after learning, the firing time of an output neuron reflects the distance of the evaluated pattern to its learned input pattern thus realizing a kind of RBF neuron. Further in the paper, we show that temporal spike-time coding and Hebbian learning is a viable means for unsupervised computation in a network of spiking neurons, as the network is capable of clustering realistic data. The modular neuron structure, the multiplier- less, fully parallel FPGA hardware implementation of the network, the acquired signals during and after the learning phase are given, with the proper interpretation of the results compared to other reported results in the specific literature.