Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates

Author

Yin, Haizhou ; Ren, Z. ; Chen, H. ; Holt, J. ; Liu, X. ; Sleight, J.W. ; Rim, K. ; Chan, V. ; Fried, D.M. ; Kim, Y.H. ; Chu, J.O. ; Greene, B.J. ; Bedell, S.W. ; Pfeiffer, G. ; Bendernagel, R. ; Sadana, D.K. ; Kanarsky, T. ; Sung, C.Y. ; Ieong, M. ; Shahi

Author_Institution

Syst. & Technol. Group, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY

fYear

0

fDate

0-0 0

Firstpage

76

Lastpage

77

Abstract

Various local stress techniques have been integrated on strained-Si directly on insulator (SSDOI) substrates, including dual stress liner (DSL), stress memory technique (SMT), and embedded SiGe (eSiGe) in source/drain. SMT shows mild drive current enhancement on nFETs. PFETs with eSiGe exhibit significant enhancement, suggesting eSiGe compatibility with SSDOI is excellent. A ring oscillator delay of 3ps is achieved at leakage current of 1 muA/mum and V_DD=1.1V

Keywords

Ge-Si alloys; field effect transistors; leakage currents; silicon-on-insulator; stress analysis; 1.1 V; 3 ps; PFET; SiGe; dual stress liner; leakage current; local stress techniques; nFET; ring oscillator delay; strained-silicon directly on insulator substrates; stress memory technique; CMOS technology; Compressive stress; DSL; Germanium silicon alloys; Insulation; Silicon germanium; Substrates; Surface-mount technology; Tensile strain; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705224

Filename

1705224