Stress Memorization Technique (SMT) Optimization for 45nm CMOS

Author

Ortolland, C. ; Morin, P. ; Chaton, C. ; Mastromatteo, E. ; Populaire, C. ; Orain, S. ; Leverd, F. ; Stolk, P. ; Boeuf, F. ; Arnaud, F.

Author_Institution

Philips Semicond., Crolles

fYear

0

fDate

0-0 0

Firstpage

78

Lastpage

79

Abstract

In this paper, we present an optimization path of stress memorization technique (SMT) for 45nm node and below using a nitride capping layer. We demonstrate that the understanding of coupling between nitride properties, dopant activation and poly-silicon gate mechanical stress allows enhancing nMOS performance by 7% without pMOS degradation. In contrast to previously reported works on SMT (Chen et al., 2004) - (Singh et al., 2005), a low-cost process compatible with consumer electronics requirements has been successfully developed

Keywords

CMOS integrated circuits; plasma materials processing; semiconductor doping; stress analysis; 45 nm; CMOS; dopant activation; nMOS; nitride capping layer; nitride properties; pMOS; poly-silicon gate mechanical stress; stress memorization; Capacitance; Circuits; Consumer electronics; Degradation; Hydrogen; MOS devices; Mechanical factors; Silicon compounds; Stress; Surface-mount technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705225

Filename

1705225