An Effort-Minimized DFT Scheme for Microcontroller Aimed at In-System Test

This paper presents a DFT scheme which combines boundary scan with built-in self test for microcontrollers. It focuses on mutual effects between the significant steps in design process and DFT tasks. The steps includes power reduction application in front-end design, discontinuous static timing analysis and clock tree synthesis in back-end design. Our circuit modification for power reduction guarantees the latch\´s transparence and avoid unacceptable "X" value in logic build-in self test. An improved test point insertion method helps to prevent repetitious logic BIST insertion and static timing analysis. Simple test clock strategy brings out clock tree generation trouble, through change the position of the clock selection logic for DFF who is driven by different clock at different mode, it is resolved perfectly. Based on the experiment on a 450 k gates aerospace application microcontroller, the feasibility of the scheme above is verified.