A Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation Induced Stress for 45-nm Node

Author

Le Cam, C. ; Guyader, F. ; de Buttet, C. ; Guyader, P. ; Ribes, G. ; Sardo, M. ; Vanbergue, S. ; Boeuf, F. ; Arnaud, F. ; Josse, E. ; Haond, M.

Author_Institution

Philips Semicond., Crolles

fYear

0

fDate

0-0 0

Firstpage

82

Lastpage

83

Abstract

This paper demonstrates, for the first time, that sub-atmospheric chemical vapour deposition (SACVD) oxide is a good candidate for 45-nm node as shallow trench isolation (STI) gap-fill as well as a mobility enhancement technique for both lang100rang and lang110rang channel orientations. Respectively, 11% and 18% drive current enhancement for NMOS and PMOS transistors as well as a 12% ring oscillator speed improvement compared to a conventional high density plasma (HDP) process are reported

Keywords

MOSFET; chemical vapour deposition; isolation technology; plasma materials processing; 45 nm; NMOS transistors; PMOS transistors; drive current enhancement; high density plasma process; mobility enhancement; ring oscillator speed improvement; shallow trench isolation induced stress; subatmospheric chemical vapour deposition; Annealing; Chemical vapor deposition; Costs; MOS devices; MOSFETs; Plasma chemistry; Plasma density; Ring oscillators; Stress; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705227

Filename

1705227