Suppression Effects of Threshold Voltage Variation with Ni FUSI Gate Electrode for 45nm Node and Beyond LSTP and SRAM Devices

Author

Okayama, Y. ; Saito, Takashi ; Nakajima, Kensuke ; Taniguchi, Shinji ; Ono, Takahito ; Nakayama, Keisuke ; Watanabe, Ryuji ; Oishi, A. ; Eiho, A. ; Komoda, Toshiya ; Kimura, Tomohiro ; Hamaguchi, Mutsumi ; Takegawa, Yoshinari ; Aoyama, Tadayoshi ; Iinuma,

Author_Institution

Syst. LSI Div., Toshiba Corp., Yokohama

fYear

0

fDate

0-0 0

Firstpage

96

Lastpage

97

Abstract

We have found that fully silicided (FUSI) gate is a promising technology for the first time not only for breaking the gate stack scaling limitation on low standby power (LSTP) devices but for keeping continuous scaling of high density SRAM (HDSRAM) for 45nm node and beyond. It is shown that FUSI will drastically suppress the fluctuation of threshold voltage (Vth) of fine transistors of HDSRAM. We have confirmed that FUSI gate drastically decreases the Vth variation which is caused by high impurity concentration of channel region and inter-diffusion of gate doping between nMOSFET and pMOSFET, both are essential and unable to be avoided. These parts of Vth fluctuation are suppressed to the degree that HDSRAM will be scaled on the ongoing trend by utilizing FUSI gate

Keywords

MOSFET; SRAM chips; electrodes; transistors; 45 nm; LSTP devices; Ni; SRAM devices; fine transistors; fully silicided gate electrode; gate stack scaling limitation; high density SRAM; nMOSFET; pMOSFET; suppression effects; threshold voltage variation; Counting circuits; Degradation; Doping; Electrodes; Fluctuations; Impurities; MOS devices; MOSFET circuits; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705234

Filename

1705234