A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Author

Yuan, J. ; Tan, S.S. ; Lee, Y.M. ; Kim, J. ; Lindsay, R. ; Sardesai, V. ; Hook, T. ; Amos, R. ; Luo, Z. ; Lee, W. ; Fang, S. ; Dyer, T. ; Rovedo, N. ; Stierstorfer, R. ; Yang, Z. ; Li, J. ; Barton, K. ; Ng, H. ; Sudijono, J. ; Ku, J. ; Hierlemann, M. ; Sc

Author_Institution

Semicond. Res. & Dev. Center, IBM, Hopewell Junction, NY

fYear

0

fDate

0-0 0

Firstpage

100

Lastpage

101

Abstract

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well

Keywords

MOSFET; leakage currents; low-power electronics; nanoelectronics; 1.2 V; 45 nm; NMOS; PMOS; asymmetric input-output; gate-induced-drain-leakage reduction; integrated dual-stress-liner technology; low power technology; stress-proximity-technique; Compressive stress; Costs; DSL; Gate leakage; Implants; MOS devices; Performance gain; Research and development; Semiconductor device manufacture; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-0005-8

Type

conf

DOI

10.1109/VLSIT.2006.1705236

Filename

1705236