A flexible design of network on chip router based on handshaking communication mechanism

One of the important issues in power and performance trade off analysis in network on chip designs is communication. Communication portion in the power consumption of system on chip can be up to 50% of the whole power of consumption of the chip. This deems to be more important for network on chips which center around an intercommunication networks. Many networks on chip routers have been designed; however most of them have not been implemented until now. In this paper, design and implementation of a synchronous network on chip router based on asynchronous communication mechanism are presented. We designed a router with scalability feature which is synthesized in both FPGA and ASIC infrastructures. In addition, the proposed router uses low resource utilization percentage of FPGA and ASIC.