28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and <-100dBc reference spur for 802.11ac

Conventional analog PLLs do not scale well with process when compared to all-digital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop filter size, while the out-of-band noise is reduced by improving VCO tank Q; both lead to increased die area. This paper presents a fractional-N synthesizer targeting the relatively stringent phase noise requirement to support 256-QAM and MIMO in 802.11ac. It deploys the following techniques to simultaneously address requirements of compact area, low noise and fast calibration: reuse of VCO inductor area for the loop filter; a PFD and CP design that relaxes CP design constraints without sacrificing noise; inductor-less LO generation for 802.11bgn mode; and an area-efficient reference clock doubler and associated calibration scheme. The synthesizer block diagram is shown in Fig. 28.2.1. In 802.11ac/a mode a frequency tripler followed by I/Q dividers realizes the 3/2 frequency multiplication and I/Q generation. In 802.11bgn mode, an LO generation circuit performs the 2/3 frequency multiplication and I/Q generation. This frequency plan features overlapping VCO tuning ranges between 802.11ac/a (F_LO=4915~5825MHz) and 802.11bgn (F_LO=2412~2484MHz) modes, such that the VCO designed for 802.11ac/a can support 802.11bgn without additional tuning range.