The trigger system for the drift chamber of BESIII

This paper describe the scheme design and hardware implementation of trigger system for drift chamber of BESIII, the key part of the trigger system of BESIII. The selection of trigger conditions and the capability of trigger efficiency and background rejection were studied carefully by simulation. Optical link was designed between the FEE and the trigger processor for complete electrical isolation avoiding ground loops and common mode problems. On-chip serial/deserial transceiver embedded in FPGA was used to enhance integration and stability. The long-term data taking had proved the operation stability and reliability of the system, demonstrated the good operation performance of each subsystem and the good integrated performance of the whole system, and fulfilled the request of BESIII.