Title :
30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology
Author :
Gathman, Timothy D. ; Madsen, Kristian N. ; Li, James C. ; Oh, Thomas C. ; Buckwalter, James F.
Author_Institution :
Qualcomm, San Diego, CA, USA
Abstract :
High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while retaining high-speed performance.
Keywords :
BiCMOS analogue integrated circuits; CMOS analogue integrated circuits; III-V semiconductors; amplifiers; analogue-digital conversion; heterojunction bipolar transistors; indium compounds; optical communication; sample and hold circuits; switching circuits; timing circuits; BiCMOS technology; HBT; InP; THA; bit rate 100 Gbit/s; distortion performance; double-switching high speed track-and-hold amplifier; frequency response; high-speed CMOS analog-to-digital converter; high-speed high-resolution data converter; high-speed time-interleaved ADC; optical communication system; packaging; timing requirement; BiCMOS integrated circuits; CMOS integrated circuits; Heterojunction bipolar transistors; Indium phosphide; Linearity; Nonlinear distortion; Switches;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-0918-6
DOI :
10.1109/ISSCC.2014.6757530
