A silicon pixel readout ASIC in CMOS 0.13 μm for the PANDA microvertex detector

The requirements for the PANDA Micro Vertex Detector in terms of track density and absence of a trigger signal lead to the need of a custom solution for the electronic readout of the silicon pixel detectors. A reduced scale prototype with two 128 cells and two 32 cells columns has been designed in a CMOS 0.13 μm technology and successfully tested. The ASIC measures the 2-D position, the hit arrival time and the charge released via a Time over Threshold technique.